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Mentor Graphics Corporation v. EVE-USA, Inc.

United States District Court, D. Oregon, Portland Division

March 6, 2014

MENTOR GRAPHICS CORPORATION, an Oregon Corporation, Plaintiff/Counter-defendant,
v.
EVE-USA, INC., a Delaware corporation; and SYNOPSYS EMULATION AND VERIFICATION S.A., formed under the laws of France, Defendants/Counter-claimants. SYNOPSYS, INC., a Delaware corporation; EVE-USA, INC., a Delaware corporation; and SYNOPSYS EMULATION AND VERIFICATION S.A., formed under the laws of France, Plaintiffs/Counter-defendants
v.
MENTOR GRAPHICS CORPORATION, an Oregon corporation, Defendant/Counter-claimant.

OPINION AND ORDER

MICHAEL W. MOSMAN, District Judge.

On February 24, 2014, I held a claim construction hearing in the above-entitled patent actions. At issue were claim terms appearing in U.S. Patent Nos. 7, 069, 526 ("'526 patent"), 6, 240, 376 ("'376 patent"), 5, 649, 176 ("'176 patent"), 6, 009, 531 ("'531 patent), and 6, 947, 882 ("'882 patent"). In this Order, I announce my constructions of the following terms:

Claim Term Construction '526 Patent "monitoring the entire or partial state of the DUT at, and relative to, design visibility predetermined events" "altering the behavior of the DUT to a predetermined particular design patching desired state at predetermined events" "methods to specify the events that control design visibility and design design control patching" instrumentation circuitry "additional circuitry to facilitate debugging" aspect "portion" integrated circuit "one or more manufactured or configured chips that implement a product design in the target technology" '376 Patent gate-level netlist "a list of gates and their inputs, outputs, and interconnects" gate-level design "a list of gates and their inputs, outputs, and interconnects" "output signal added or preserved during logic synthesis that indicates instrumentation signal whether a corresponding RTL source code statement is active" simulating a gate-level "modeling the operation of a gate level design using software and/or design hardware" sensitivity list "a list of signals to which a process is responsive" process "a description of the behavior of some portion of a circuit design" generating logic "generating gates" '176 and '531 Patents "a system including one or more configurable logic devices into which logic system the circuit design under test is configured" configurable logic "a system including one or more configurable logic devices into which system the circuit design under test is configured" "a real or simulated system or circuit, external to the configurable logic system, in which the circuit design under test is intended to environment operate"

"a timing signal, originating from the environment and received by the environmental timing logic system, with a frequency that is lower than the internal clock signal frequency" "a signal existing within the configurable logic system and invisible to the environment that provides a time base for scheduling the operation internal clock signal of the resynthesized circuit" '882 Patent reconfigurable logic "chip that includes a plurality of reconfigurable logic elements and device input/output circuitry" first plurality of "two or more reconfigurable logic devices, none of which are included reconfigurable logic in the second plurality of reconfigurable logic devices or the third devices plurality of reconfigurable logic devices" second plurality of "two or more reconfigurable logic devices, none of which are included reconfigurable logic in the first plurality of reconfigurable logic devices or the third devices plurality of reconfigurable logic devices" third plurality of "two or more reconfigurable logic devices, none of which are included reconfigurable logic in the first plurality of reconfigurable logic devices or the second devices plurality of reconfigurable logic devices" interconnect device This term no longer appears in any patent claim at issue. "structure capable of receiving data from each reconfigurable logic time multiplexed device in one plurality and transmitting the data to each reconfigurable interconnection logic device in another plurality" "independent" "wherein there is no required timing relationship between clock clocking edges"[1] circuit design "a design for an integrated circuit" "a system capable of reproducing the operation of a circuit design emulation system through steps including mapping the circuit design onto hardware" "a system capable of reproducing the operation of a circuit design emulator through steps including mapping the circuit design onto hardware"

IT IS SO ORDERED.


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